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data sheet ics843s104bki-133 revision a june 9, 2009 1 ?2009 integrated device technology, inc. crystal-to-lvpecl 133mhz clock synthesizer ICS843S104I-133 general description the ICS843S104I-133 is a pll-based clock synthesizer specifically designed for low phase noise applications. this device generates a 133.33mhz differential lvpecl clock from an input reference of 25mhz. the input reference may be derived from an external source or by the addition of a 25mhz crystal to the on-chip crystal oscillator. an external reference is applied to the pclk, npclk pins.the device offers spread spectrum clock output for reduced emi applications. an i 2 c bus interface is used to enable or disable spread spectrum operation as well as to select either a down spread value of -0.35% or -0.5%.the ICS843S104I-133 is available in a lead-free 32-lead vfqfn package. features ? four lvpecl ou tput pairs ? crystal oscillator interface: 25mhz ? differential pclk/npclk input pair ? pclk/npclk supports the following input types: lvpecl, cml, sstl ? output frequency: 133.33mhz ? pci express (2.5 gb/s) and ge n 2 (5 gb/s) jitter compliant ? rms phase jitter @ 133.33mhz (12khz ? 20mhz): 1.2ps (typical) ? i 2 c support with readback capabilities up to 400khz ? spread spectrum for electromagnetic interference (emi) reduction ? 3.3v operating supply mode ? -40c to 85c ambient operating temperature ? available lead-free (rohs 6) package hiperclocks? ic s pll osc i 2 c logic q[1:4] nq[1:4] pullup pullup pullup/pulldown pulldown pulldown xtal_in xtal_out s data pclk npclk ref_sel sclk 25mhz 1 0 4 4 ICS843S104I-133 32-lead vfqfn 5.0mm x 5.0mm x 0.925mm package body k package top view pin assignment 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v cc ref_sel v ee pclk npclk v ee v cca v ee v ee nq3 q3 v cc v ee nq4 q4 v cc v ee v ee v cc_xosc xtal_in xtal_out nc sclk sdata nq1 q1 v cc v cc nq2 q2 v cc v ee block diagram
ics843s104bki-133 revision a june 9, 2009 2 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer table 1. pin descriptions note: pullup and pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 17, 21, 25, 28, 29 v cc power core supply pins. 2 ref_sel input pulldown select input for xtal (low) or ref_in (high). lvcmos/lvttl interface levels. 3, 6, 8, 9, 10, 20, 24, 32 v ee power negative power supply pins. 4 pclk input pulldown non-inverting external 25mhz differential reference input. lvpecl input levels. 5 npclk input pullup/ pulldown inverting external 25mhz differential reference input. lvpecl input levels. 7v cca power analog supply for pll. 11 v cc_xosc power analog supply for crystal oscillator. 12, 13 xtal_in, xtal_out input crystal oscillator interface. xta l_in is the input. xtal_out is the output. 14 nc unused no connect. 15 sclk input pullup i 2 c compatible sclk. this pin has an internal pullup resistor. lvcmos/lvttl interface levels. 16 sdata i/o pullup i 2 c compatible sdata. this pin has an internal pullup resistor. lvcmos/lvttl interface levels. 18,19 q4, nq4 outpu t differential output pair. lvpecl interface levels. 22, 23 q3, nq3 output diffe rential output pair. l vpecl interface levels. 26, 27 q2, nq2 output diffe rential output pair. l vpecl interface levels. 30, 31 q1, nq1 output diffe rential output pair. l vpecl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics843s104bki-133 revision a june 9, 2009 3 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal i 2 c serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial interface initialize to their default settings upon power-up, and therefore, use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. data protocol the clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. for block write/read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 3a. the block write and block read protocol is outlined in table 3b, while table 3c outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 3a.command code definition bit 7 6, 5 4:0 description 0 = block read or block write operation, 1 = byte read or byte write operation. chip select address, set to ?00? to access device. byte offset for byte read or byte write operation. for block read or block write operations, these bits must be ?00000?.
ics843s104bki-133 revision a june 9, 2009 4 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer table 3b. block read and block write protocol table 3c. byte read and byte write protocol bit description = block writ e bit description = block read 1start 1start 2:8 slave address - 7 bits 2:8 slave address - 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code - 8 bits 11:18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count - 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address - 7 bits 29:36 data byte 1 - 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 2 - 8 bits 30:37 byte count from slave - 8 bits 46 acknowledge from slave 38 acknowledge data byte/slave acknowledges 39:46 data byte 1 from slave - 8 bits data byte n - 8 bits 47 acknowledge acknowledge from slave 48:55 data byte 2 from slave - 8 bits stop 56 acknowledge data bytes from slave/acknowledge data byte n from slave - 8 bits not acknowledge stop bit description = byte write bit description = byte read 1 start 1 start 2:8 slave address - 7 bits 2:8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code - 8 bits 11:18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte - 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address - 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data from slave - 8 bits 38 not acknowledge 39 stop
ics843s104bki-133 revision a june 9, 2009 5 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer control registers table 3d. byte 0: control register 0 table 3e. byte 1: control register 1 table 3f. byte 2: control register 2 table 3g. byte 3:control register 3 table 3h. byte 4: control register 4 table 3i. byte 5: control register 5 bit @powerup name description 7 0 reserved reserved 61 q4en q4, nq4 output enable 0 = low 1 = enable 51 q3en q3, nq3 output enable 0 = low1 = enable 41 q2en q2, nq2 output enable 0 = low 1 = enable 31 q1en q1, nq1 output enable 0 = low 1 = enable 2 1 reserved reserved 1 0 reserved reserved 0 0 reserved reserved bit @powerup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved bit @powerup name description 7 1 ss_sel spread spectrum selection 0 = -0.35%, 1 = - 0.5% 6 1 reserved reserved 5 1 reserved reserved 4 0 reserved reserved 3 1 reserved reserved 2 0 ssm q spread spectrum enable 0 = spread off, 1 = spread on 1 1 reserved reserved 0 0 reserved reserved bit @powerup name description 7 1 reserved reserved 6 0 reserved reserved 5 1 reserved reserved 4 0 reserved reserved 3 1 reserved reserved 2 1 reserved reserved 1 1 reserved reserved 0 1 reserved reserved bit @powerup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 1 reserved reserved bit @powerup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved
ics843s104bki-133 revision a june 9, 2009 6 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer table 3j. byte 6: control register 6 table 3k. byte 7: control register 7 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c bit @powerup name description 7 0 test_sel ref/n or hi-z select 0 = hi-z, 1 = ref/n 6 0 test_mode test clock mode entry control 0 = normal operation, 1 = ref/n or hi-z mode 5 0 reserved reserved 4 1 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 1 reserved reserved 0 1 reserved reserved bit @powerup name description 7 0 revision code bit 3 6 0 revision code bit 2 5 0 revision code bit 1 4 0 revision code bit 0 3 0 vendor id bit 3 2 0 vendor id bit 2 1 0 vendor id bit 1 0 1 vendor id bit 0 item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma package thermal impedance, ja 39.5 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.22 3.3 v cc v v cc_xosc analog supply voltage v cc ? 0.05 3.3 v cc v i ee power supply current 130 ma i cca analog supply current 22 ma i cc_xosc crystal oscillator supply current 5ma
ics843s104bki-133 revision a june 9, 2009 7 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer table 4b. lvcmos/lvttl dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c table 4c. lvpecl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c) note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . note 3: outputs terminated with 50 ? to v cc ? 2v. table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage sdata, sclk 2.0 v cc + 0.3 v v il input low voltage sdata, sclk 1.7 v cc + 0.3 v i ih input high current sdata, sclk v cc = v in = 3.465v 10 a ref_sel v cc = v in = 3.465v 150 a i il input low current sdata, sclk v cc = 3.465v, v in = 0v -150 a ref_sel v cc = 3.465v, v in = 0v -10 a symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 3.465v 150 a i il input low current pclk v cc = 3.465v, v in = 0v -10 a npclk v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak volt age; note 1 0.3 1.0 v v cmr common mode input vo ltage; note 1, 2 v ee + 1.5 v cc v v oh output high voltage; note 3 v cc ? 1.3 v cc ? 0.8 v v ol output low voltage; note 3 v cc ? 2.0 v cc ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics843s104bki-133 revision a june 9, 2009 8 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer ac electrical characteristics table 6. ac characteristics, v cc = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions.. note 1: please refer to phase noise plot. note 2: peak-to-peak jitter after applying system transfer func tion for the common clock architecture. maximum limit for pci ex press gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. see idt application note pci express reference clock requirements and also the pci express application section of this datasheet which sh ow each individual transfer function and the overall composite tr ansfer function. note 3: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architectu re and reporting the worst case results for each evaluation band. maxi mum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0 ps rms for t refclk_lf_rms (low band). see idt application note pci express reference clock requirements and also the pci express application section of this datasheet which sh ow each individual transfer function and the overall composite tr ansfer function. symbol parameter test conditio ns minimum typical maximum units f max output frequency 133.33 mhz f ref reference frequency 25 mhz t jit(?) rms phase jitter, (random); note 1 ssc off, integration range: 12khz ? 20mhz 1.2 ps t j phase jitter peak-to-peak; note 2 evaluation band: 0hz - nyquist (clock frequency/2) 11 ps t refclk_hf_rms phase jitter rms; note 3 133.33mhz 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2 1.3 ps t refclk_lf_rms phase jitter rms; note 3 133.33mhz 25mhz crystal input low band: 10khz - 1.5mhz 0.21 ps odc output duty cycle 49 51 % t r / t f output rise/fall time 100 250 ps
ics843s104bki-133 revision a june 9, 2009 9 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer typical phase noise at 133.33mhz noise power dbc offset frequency (hz) 133.33mhz rms phase jitter (random) 12khz to 20mhz = 1.2ps (typical)
ics843s104bki-133 revision a june 9, 2009 10 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer parameter measureme nt information 3.3v lvpecl output load ac test circuit rms phase jitter differential input level output duty cycle/pulse width/period rise/fall time scope qx nqx lvpecl v ee v cca v cc 2v 2v -1.3v 0.165v 2v v cc_xosc phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 20% 80% 80% 20% t r t f v swing nq[1:4] q[1:4] v cc v ee v cmr cross points v pp npclk pclk t pw t period t pw t period odc = x 100% nq[1:4] q[1:4]
ics843s104bki-133 revision a june 9, 2009 11 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ICS843S104I-133 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cc_xosc and v cca should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v cca pin. figure 1. power supply filtering recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullup and pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. pclk/npclk inputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. v cc v cca v cc_xosc 3.3v 10 ? 10 ? 10f .01f .01f 10f .01f
ics843s104bki-133 revision a june 9, 2009 12 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer crystal input interface the ICS843S104I-133 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 2. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 22p c2 22p xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v dd v dd
ics843s104bki-133 revision a june 9, 2009 13 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer lvpecl clock input interface the pclk /npclk accepts l vpecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from anothe r vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4a. hiperclocks pclk/npclk input driven by a cml driver figure 4c. hiperclocks pclk/npclk input driven by a 3.3v lvpecl driver figure 4e. hiperclocks pclk/npclk input driven by a 3.3v lvds driver figure 4b. hiperclocks pclk/npclk input driven by a built-in pullup cml driver figure 4d. hiperclocks pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 4f. hiperclocks pclk/npclk input driven by an sstl driver pclk npclk hiperclocks pclk/npcl k cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl hiperclocks input 3.3v r1 100 lvds pclk npclk 3.3v hiperclocks zo = 50 ? zo = 50 ? 3.3v r1 100 cml built-in pullup pclk npclk 3.3v hiperclocks pclk/npclk zo = 50 ? zo = 50 ? r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 pclk npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v hiperclocks pclk/npclk c1 c2 pclk npclk hiperclocks pclk/npclk sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics843s104bki-133 revision a june 9, 2009 14 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. th erefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics843s104bki-133 revision a june 9, 2009 15 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics843s104bki-133 revision a june 9, 2009 16 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer schematic example figure 7 shows an example of ICS843S104I-133 application schematic. in this example, the device is operated at v cc = 3.3v. the 18pf parallel resonant 25mhz cr ystal is used. the c1 and c2 = 22pf are recommended for frequency accuracy. for different board layouts, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. for the lvpecl output drivers, only two termination examples are shown in this schematic. additional termination approaches are show n in the lvpecl termination application note. figure 7. ICS843S104I-133 schematic layout 3.3v vcc r14 50 r15 50 zo = 50 ohm vcc zo = 50 ohm + - r13 50 xtal_in pclk npclk nq1 q1 xtal_out ref_sel j1 1 2 3 4 5 (u1:17) (u1:1) (u1:21) (u1:28) (u1:25) (u1:29) r10 10 r2 133 r6 82.5 + - ru2 not install ru1 1k c2 22pf r1 133 rd2 1k rd1 not install x1 25mhz zo = 50 ohm zo = 50 ohm c1 22pf r5 82.5 vcc vcc optional y-termination vcc=3.3v u1 ICS843S104I-133 vcc 1 ref_sel 2 vee 3 pclk 4 npclk 5 vee 6 vcca 7 vee 8 vee 9 vee 10 vcc_xosc 11 xtal_in 12 xtal_out 13 nc 14 sclk 15 sdata 16 vcc 17 q4 18 nq4 19 vee 20 vcc 21 q3 22 nq3 23 vee 24 vee 32 nq1 31 q1 30 vcc 29 vcc 28 nq2 27 q2 26 vcc 25 1 8 p f vcc c3 10u c6 0.01u c5 10u r9 10 vcc vcca set logic input to '0' set logic input to '1' to logic input pins logic control input examples c7 0.1u to logic input pins c8 0.1u c9 0.1u c10 0.1u c11 0.1u c12 0.1u zo = 50 lvpecl driv er zo = 50 r7 84 vcc r8 84 r4 125 r3 125 sdata r17 sp r11 sp sclk vcc r12 sp vcc r16 sp vcc_xosc c4 0.01u q4 lvpecl termination nq4
ics843s104bki-133 revision a june 9, 2009 17 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer pci express application note pci express jitter analysis me thodology models the system response to reference clock jitter. the below block diagram shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the tx and rx serdes plls are modeled as well as the phase interpolator in the re ceiver. these transfer functions are called h1, h2, and h3 respective ly. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. for pci express gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz to 50mhz) and the jitter result is reported in peak-peak. for pci express gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz - 1.5mhz (low band) and 1.5mhz - nyquist (high band). the below plots show the individual transfer functions as well as the overall transfer function ht. the respective -3 db pole frequencies for each transfer function are labeled as f1 for transfer function h1, f2 for h2, and f3 for h3. for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s () h3 s () h1 s () h2 s () ? [] = ys () xs () h3 s () h1 s () h2 s () ? [] =
ics843s104bki-133 revision a june 9, 2009 18 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer pcie gen 1. magnitude of transfer function pcie gen 2a. magnitude of transfer function pcie gen 2b. magnitude of transfer function 10 3 10 4 10 5 10 6 10 7 -60 -50 -40 -30 -20 -10 0 frequency (hz) mag (db) magnitude of transfer functions - pcie gen 1 f1: 2.2e+007 f2: 1.5e+006 f3: 1.5e+006 h1 h2 h3 ht=(h1-h2)*h3 10 3 10 4 10 5 10 6 10 7 -60 -50 -40 -30 -20 -10 0 frequency (hz) mag (db) magnitude of transfer functions - pcie gen 2a f1: 1.6e+007 f2: 5.0e+006 f3: 1.0e+006 h1 h2 h3 ht=(h1-h2)*h3 10 3 10 4 10 5 10 6 10 7 -60 -50 -40 -30 -20 -10 0 frequency (hz) mag (db) magnitude of transfer functions - pcie gen 2b f1: 1.6e+007 f2: 8.0e+006 f3: 1.0e+006 h1 h2 h3 ht=(h1-h2)*h3
ics843s104bki-133 revision a june 9, 2009 19 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer power considerations this section provides information on power dissipati on and junction temperatur e for the ICS843S104I-133. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS843S104I-133 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 130ma = 450.45mw power (outputs) max = 32mw/loaded output pair if all outputs are loaded, the total power is 4 * 32mw = 128mw total power_ max (3.3v, with all outputs swit ching) = 450.45mw + 128mw = 578.45mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 39.5c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.578w * 39.5c/w = 107.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resitance ja for 32 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 39.5c/w 34.5c/w 31.0c/w
ics843s104bki-133 revision a june 9, 2009 20 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 8. figure 8. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.8v (v cc_max ? v oh_max ) = 0.8v for logic low, v out = v ol_max = v cc_max ? 1.6v (v cc_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.8v)/50 ? ] * 0.8v = 19.2mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.6v)/50 ? ] * 1.6v = 12.8mw total power dissipation per output pair = pd_h + pd_l = 32mw v out v cc v cc - 2v q1 rl 50
ics843s104bki-133 revision a june 9, 2009 21 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer reliability information table 8. ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ICS843S104I-133 is: 11,927 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 39.5c/w 34.5c/w 31.0c/w
ics843s104bki-133 revision a june 9, 2009 22 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer package outline and package dimensions package outline - k suffix for 32 lead vfqfn note: the following package mechanical drawing is a generic drawin g that applies to any pin count vfqfn package. this drawing i s not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9 below. table 9. package dimensions reference document: jede c publication 95, mo-220 jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or
ics843s104bki-133 revision a june 9, 2009 23 ?2009 integrated device technology, inc. ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843s104bki-133lf ics04bi133l ?lead-free? 32 lead vfqfn tray -40 c to 85 c 843s104bki-133lft ics04bi133l ?lead-free? 32 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS843S104I-133 data sheet crystal-to-lvpecl 133mhz clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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